WM8955L
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The PLL frequencyratio R = f 2/f1(see diagram above) can be set using K and N in registers 44 (2Ch)
to 46 (2Eh):
N = int (R)
K = int (222 (R-N))
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R44 (2Ch)
8:5
N
01000
Integer part of PLL input/output
frequencyratio. Use values greater
than 5 and less than 13.
PLL Control (1)
3:0
8:0
K [21:18]
K [17:9]
0011
024h
Fractional part of PLL input/output
frequencyratio (treat as one 22-digit
binarynumber)
R45 (2Dh)
PLL Control (2)
R46 (2Eh)
TBD
K [8:0]
1BAh
PLL Control (3)
Table 20 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stabilitypeaks at N=8. Some example settings
are shown below.
MCLK DESIRED
F2
MCLK
DIV2
PLL
OUT
DIV2
CLK
OUT
DIV2
R
F2
K
OUTPUT
(MHz)
(MHz)
(Hex)
(Hex)
(MHz)
11.91
11.91
12
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.5833
8.2539
7.5264
8.192
7
8
7
8
6
7
6
6
9
A
9
9
9
9
7
8
6
7
6
7
25545C
103FF6
21B089
C49BA
3CA2F4
23F548
116872
34E818
1A1CAC
F5C28
12
13
6.9474
7.5618
6.272
13
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
6.8267
9.408
10.24
9.1785
9.9902
9.1229
9.9297
7.5264
8.192
B6D22
3F6017
7DDCA
3B8023
21B089
C49BA
3CA2F4
23F548
2C2B30
12089E
24
26
6.9474
7.5618
6.6901
7.2818
26
27
27
Table 21 PLL Frequency Examples
Product Preview Rev 0.4 May2003
30
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
