Product Preview
WM8955L
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Data Word Length (WL)
Note: Word length is defined bythe WL register.
Timing is shown with LRP = 1
Figure 11 Right JustifiedAudio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a DACLRC transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequencyand sample rate, there maybe unused BCLK cycles between the LSB of one sample and
the MSB of the next.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
1 BCLK
1 BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Note: Word length is defined bythe WL register.
Timing is shown with LRP = 1
Data Word Length (WL)
Figure 12 I2S JustifiedAudio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the first or second rising edge of BCLK
(selectable byLRP) following a rising edge of DACLRC. Right channel data immediatelyfollows left
channel data. Depending on word length, BCLK frequencyand sample rate, there maybe unused
BCLK cycles between the LSB of the right channel data and the next sample.
1/fs
1 BCLK
DACLRC
BCLK
RIGHT CHANNEL
n-2 n-1
LEFT CHANNEL
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
MSB
LSB
Data Word Length (WL)
Note: Word length is defined bythe WL register.
Timing is shown with LRP = 1
Figure 13 DSP Mode Audio Interface (Mode A; LRP = 0)
Product Preview Rev 0.4 May2003
27
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
