WM8955L
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1/fs
1 BCLK
DACLRC/
ADCLRC
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n-2 n-1
n
n-2 n-1
MSB
LSB
Input Word Length (WL)
Figure 14 DSP Mode Audio Interface (Mode B; LRP = 1)
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
1:0
FORMAT
10
Audio Data Format Select
Digital Audio
Interface
Format
11 = DSP Mode
10 = I2S Format
01 = Left justified
00 = Right justified
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
3:2
WL
10
0
01 = 20 bits
00 = 16 bits
4
LRP
I2S, LJ, RJ Formats
DSP Format
1: Right Channel data 1: MSB available on
when DACLRC high
2nd BCLK rising edge
after LRC rising edge
0: Right Channel data
when DACLRC low
0: MSB available on
1st BCLK rising edge
after LRC rising edge
5
6
7
LRSWAP
MS
0
0
0
Swap Left and Right Channels
0: No swap (L to L, R to R)
1: Swap (L to R, R to L)
Master / Slave Mode Control
1: Master Mode
0: Slave Mode
BCLKINV
BCLK Invert
1: BCLK inverted
0: BCLK not inverted
Table 18 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual
word length will be 24 bits.
Product Preview Rev 0.4 May2003
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
