WM8945
Production Data
Figure 6 Control Interface Timing – 3-wire (SPI) Control Mode (Write Cycle)
Note: The data is latched on the 32nd falling edge of SCLK after 32 bits have been clocked into the device.
Figure 7 Control Interface Timing – 3-wire (SPI) Control Mode (Read Cycle)
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,
TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
C¯¯S falling edge to SCLK rising edge
SCLK falling edge to C¯¯S rising edge
SCLK pulse cycle time
SYMBOL
tCSU
tCHO
tSCY
MIN
40
10
200
80
80
40
10
0
TYP
MAX
UNIT
ns
ns
ns
SCLK pulse width low
tSCL
ns
SCLK pulse width high
tSCH
tDSU
tDHO
tps
ns
SDA to SCLK set-up time
ns
SDA to SCLK hold time
ns
Pulse width of spikes that will be suppressed
SCLK falling edge to SDA output transition
5
ns
tDL
40
ns
PD, May 2011, Rev 4.1
20
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
