Production Data
WM8945
CONTROL INTERFACE TIMING
Figure 5 Control Interface Timing – 2-wire (I2C) Control Mode
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,
TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
kHz
ns
SCLK Frequency
400
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
1300
600
600
600
100
ns
ns
ns
ns
SDA, SCLK Rise Time
300
300
ns
SDA, SCLK Fall Time
ns
Setup Time (Stop Condition)
Data Hold Time
600
0
ns
900
5
ns
Pulse width of spikes that will be suppressed
ns
PD, May 2011, Rev 4.1
19
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
