WM8945
Production Data
SLAVE MODE
tBCY
BCLK (input)
tBCH
tBCL
LRCLK (input)
tLRH
tLRSU
ADCDAT (output)
DACDAT (input)
tDD
tDS
tDH
Figure 4 Audio Interface Timing – Slave Mode
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,
TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
Audio Interface Timing – Slave Mode
BCLK cycle time
SYMBOL
MIN
TYP
MAX
UNIT
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
DACDAT set-up time to BCLK rising edge
tDD
20
tDS
20
Note: BCLK period must always be greater than or equal to MCLK period.
PD, May 2011, Rev 4.1
18
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
