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WM8945 参数 Datasheet PDF下载

WM8945图片预览
型号: WM8945
PDF下载: 下载PDF文件 查看货源
内容描述: 单声道低功耗编解码器与视频缓冲器和触摸屏控制器 [Mono Low-Power CODEC with Video Buffer and Touch Panel Controller]
分类和应用: 解码器编解码器控制器
文件页数/大小: 169 页 / 1604 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8945  
Production Data  
INPUT PGA ENABLE  
The input PGA (Programmable Gain Amplifiers) is enabled using the register bit INPPGAL_ENA, as  
described in Table 1.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R2 (02h)  
INPPGAL_ENA  
Left Input PGA Enable  
0 = Disabled  
12  
0
Power  
Management 1  
1 = Enabled  
Table 1 Input PGA Enable  
To enable the input PGA, the reference voltage VMID and the bias current must also be enabled. See  
“Reference Voltages and Master Bias” for details of the associated controls VMID_SEL and  
BIAS_ENA.  
INPUT PGA CONFIGURATION  
Microphone and Line level audio inputs can be connected to the WM8945 in single-ended or  
differential configurations. (These two configurations are illustrated in Figure 61 and Figure 62 in the  
section describing the external components requirements – see “Applications Information”.)  
For single-ended microphone inputs, the microphone signal is connected to the non-inverting input of  
the PGA, whilst the inverting input of the PGA is connected to VMID. For differential microphone  
inputs, the non-inverted microphone signal is connected to the non-inverting input of the PGA, whilst  
the inverted (or ‘noisy ground’) signal is connected to the inverting input pin.  
Line level inputs are connected in the same way as a single-ended microphone signal.  
The non-inverting input of the PGA is configured using the P_PGAL_SEL register. This register allows  
the selection of three possible input pins to the PGA. When the AUX1 or AUX2 pin is used as an  
audio input, that pin must be configured for audio using the AUX1_AUDIO or AUX2_AUDIO register  
bits.  
The inverting input of the PGA is configured using MICLN_TO_N_PGAL. This register allows the PGA  
to operate in either single-ended or pseudo-differential configuration.  
The registers for configuring the Input PGA are described in Table 2.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R39 (27h)  
Input Ctrl  
AUX2_AUDIO  
AUX2 pin configuration  
0 = Non-Audio signal  
8
0
1 = AC-coupled Audio signal  
AUX1 pin configuration  
0 = Non-Audio signal  
AUX1_AUDIO  
7
4
0
1
1 = AC-coupled Audio signal  
MICLN_TO_N_  
PGAL  
Left Input PGA Inverting Input  
Select  
0 = Connected to VMID  
1 = Connected to IN2L  
P_PGAL_SEL  
[1:0]  
Left Input PGA Non-Inverting Input  
Select  
1:0  
01  
00 = Connected to IN2L  
01 = Connected to IN1L  
10 = Connected to AUX1  
11 = Reserved  
Table 2 Input PGA Configuration  
PD, May 2011, Rev 4.1  
24  
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