Production Data
WM8945
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 2 Master Clock Timing
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25oC.
PARAMETER
Master Clock Timing
MCLK cycle time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
TMCLKY
0.037s
s
MCLK duty cycle
60:40
40:60
(= TMCLKH : TMCLKL
)
AUDIO INTERFACE TIMING
MASTER MODE
BCLK (Output)
LRCLK (Output)
tDL
tDDA
ADCDAT
DACDAT
tDST
tDHT
Figure 3 Audio Interface Timing – Master Mode
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,
TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Interface Timing – Master Mode
LRCLK propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
20
20
ns
ns
ns
ns
tDDA
tDST
tDHT
20
10
PD, May 2011, Rev 4.1
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
