Production Data
WM8945
Figure 49 Power-On Reset Timing – DCVDD enabled first
The P¯O¯¯R signal is undefined until LDOVDD has exceeded the minimum threshold, Vpora Once this
threshold has been exceeded, P¯O¯¯R is asserted low and the chip is held in reset. In this condition, all
writes to the control interface are ignored. Once LDOVDD and DCVDD have both reached their
respective power on thresholds, P¯O¯¯R is released high, all registers are in their default state, and
writes to the control interface may take place.
Note that a minimum power-on reset period, TPOR, applies even if LDOVDD and DCVDD have zero
rise time. (This specification is guaranteed by design rather than test.)
On power down, P¯O¯¯R is asserted low when LDOVDD or DCVDD falls below their respective power-
down thresholds.
Typical Power-On Reset parameters for the WM8945 are defined in Table 70.
SYMBOL
Vpora
DESCRIPTION
Power-On undefined threshold (LDOVDD)
Power-On threshold (LDOVDD)
Power-Off threshold (LDOVDD)
Power-On threshold (DCVDD)
Power-Off threshold (DCVDD)
Minimum Power-On Reset period
MIN
TYP
0.5
MAX
UNIT
V
Vpora_on
Vpora_off
Vpord_on
Vpord_off
TPOR
1.15
1.12
0.57
0.56
10.6
V
V
V
V
s
Table 70 Typical Power-On Reset Parameters
Separate Power-On Reset circuits are also implemented on the DBVDD and SPKVDD domains.
These circuits ensure correct device behaviour whenever these supplies are enabled or disabled.
PD, May 2011, Rev 4.1
105
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
