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WM8945 参数 Datasheet PDF下载

WM8945图片预览
型号: WM8945
PDF下载: 下载PDF文件 查看货源
内容描述: 单声道低功耗编解码器与视频缓冲器和触摸屏控制器 [Mono Low-Power CODEC with Video Buffer and Touch Panel Controller]
分类和应用: 解码器编解码器控制器
文件页数/大小: 169 页 / 1604 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8945  
Production Data  
REGISTER MAP  
REG  
NAME  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
DEFAULT  
Software Reset/Chip  
ID 1  
R0 (0h)  
SW_RESET[15:0]  
6229h  
Chip ID 2  
R1 (1h)  
R2 (2h)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHIP_REV[3:0]  
0000h  
0000h  
Power management  
1
INPPG  
AL_EN  
A
ADCL_  
ENA  
0
DMIC_  
ENA  
0
0
MICB_ BIAS_ VMID_ VMID_SEL[1:0]  
ENA ENA BUF_E  
NA  
Power management  
2
R3 (3h)  
0
OUTL_ SPKR_ SPKL_ SPKR_ SPKL_ SPKR_ SPKL_ SPKR_ SPKL_ SPKR_ SPKL_ SPKR_ SPKL_ DACR DACL_ 0330h  
ENA PGA_ PGA_ SPKV SPKV OP_M OP_M OP_E OP_E MIX_M MIX_M MIX_E MIX_E _ENA ENA  
ENA ENA DD_E DD_E UTE UTE  
NA NA  
DACDATA_PU FRAME_PULL[ BCLK_PULL[1: ADCR ADCL_  
LL[1:0] 1:0] 0] _SRC SRC  
NA  
NA  
UTE UTE  
NA  
NA  
Audio Interface  
R4 (4h)  
R5 (5h)  
1
DACL_ BCLK_ LRCLK  
WL[1:0]  
FMT[1:0]  
028Ah  
0000h  
SRC  
INV  
_INV  
Companding control  
0
0
0
0
0
0
0
0
0
0
LOOP  
BACK  
0
DAC_ DAC_ ADC_ ADC_  
COMP COMP COMP COMP  
MODE  
MODE  
Clock Gen control  
Additional control  
R6 (6h)  
R7 (7h)  
OSC_ MCLK_PULL[1: CLKO CLKOUT_DIV[1 SYSCL SYSCL  
SYSCLK_DIV[2:0]  
TOCL  
BCLK_DIV[2:0]  
MSTR  
0106h  
000Dh  
CLK_E  
NA  
0]  
UT_SE  
L
:0]  
K_ENA K_SR  
C
K_ENA  
0
0
0
0
0
0
VMID_ VMID_ VMID_ START BIAS_ VMID_RAMP[1: VMID_  
SR[3:0]  
FAST_ REF_S CTRL UP_BI SRC  
0]  
ENA  
START EL  
AS_EN  
A
FLL Control 1  
R8 (8h)  
0
FLL_CLK_REF  
_DIV[1:0]  
FLL_OUTDIV[2:0]  
FLL_CTRL_RATE[2:0]  
FLL_FRATIO[2:0]  
FLL_F FLL_E  
0102h  
RAC  
NA  
FLL Control 2  
FLL Control 3  
GPIO Config  
R9 (9h)  
FLL_K[15:0]  
3127h  
0104h  
0000h  
R10 (Ah)  
R11 (Bh)  
0
0
FLL_N[9:0]  
0
0
FLL_GAIN[3:0]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODE  
_GPIO  
GPIO1 Control  
GPIO2 Control  
GPIO3 Control  
GPIO4 Control  
System Interrupts  
Status Flags  
R12 (Ch)  
R13 (Dh)  
R14 (Eh)  
R15 (Fh)  
R16 (10h)  
R17 (11h)  
GP1_D GP1_PULL[1:0] GP1_I  
GP1_P  
OL  
0
GP1_L  
VL  
0
0
0
0
0
0
GP1_FN[3:0]  
GP2_FN[3:0]  
GP3_FN[3:0]  
GP4_FN[3:0]  
8000h  
8000h  
C000h  
8000h  
0000h  
0000h  
IR  
NT_M  
ODE  
GP2_D GP2_PULL[1:0] GP2_I  
0
0
0
GP2_P  
OL  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GP2_L  
VL  
IR  
NT_M  
ODE  
GP3_D GP3_PULL[1:0] GP3_I  
GP3_P  
OL  
GP3_L  
VL  
IR  
NT_M  
ODE  
GP4_D GP4_PULL[1:0] GP4_I  
GP4_P  
OL  
GP4_L  
VL  
IR  
NT_M  
ODE  
TEMP GP4_I GP3_I GP2_I GP1_I TCHD TCHP AUXA  
0
0
0
0
0
0
0
0
LDO_  
UV_IN  
T
_INT  
NT  
NT  
NT  
0
NT ATA_I D_INT DC_IN  
NT  
T
TEMP  
_STS  
0
0
0
0
0
0
0
0
LDO_  
UV_ST  
S
IRQ Config  
R18 (12h)  
R19 (13h)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_IR  
Q
0001h  
0000h  
System Interrupts  
Mask  
IM_TE IM_GP IM_GP IM_GP IM_GP IM_TC IM_TC IM_AU  
MP_IN 4_INT 3_INT 2_INT 1_INT HDAT HPD_I XADC  
IM_LD  
O_UV_  
INT  
T
A_INT NT  
_INT  
Control Interface  
DAC Control 1  
R20 (14h)  
R21 (15h)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPI_O SPI_4 AUTO  
0002h  
D
WIRE _INC  
0
0
0
0
DAC_  
MUTE  
ALL  
DAC_  
AUTO  
MUTE  
0
0
DACL_ 0110h  
DATIN  
V
DAC Control 2  
R22 (16h)  
0
0
0
0
0
0
0
0
0
0
DAC_  
0
0
0
DAC_  
0010h  
VOL_R  
SB_FL  
PD, May 2011, Rev 4.1  
108  
w
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