WM8945
Production Data
Figure 47 4-Wire Readback (Open Drain)
POWER MANAGEMENT
The WM8945 has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To ٛ minimise pop or click noise,
it is important to enable or disable these functions in the correct order, and to use the signal mute
registers as part of a carefully structured control sequence. Refer to the “Recommended Power
Up/Down Sequence” section for more details.
The power management control registers are described in Table 68.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
INPPGAL_ENA
Left Input PGA Enable
0 = Disabled
12
0
Power
management
1
1 = Enabled
ADCL_ENA
0
Left ADC and Record filter Enable
0 = Disabled
10
1 = Enabled
ADCL_ENA must be set to 1 when
processing left channel data from
the ADC or Digital Microphone.
MICB_ENA
BIAS_ENA
OUTL_ENA
Microphone Bias Enable
0 = Disabled
4
0
0
0
0
0
0
1 = Enabled
Master Bias Enable
0 = Disabled
3
1 = Enabled
R3 (03h)
LINEOUTL enable
0 = Disabled
14
13
12
11
Power
management
2
1 = Enabled
SPKR_PGA_
ENA
Speaker Right PGA enable
0 = Disabled
1 = Enabled
SPKL_PGA_
ENA
Speaker Left PGA enable
0 = Disabled
1 = Enabled
SPKR_SPKVDD
_ENA
SPKOUTR enable
0 = Disabled
1 = Enabled
Note that SPKOUTR is also
controlled by SPKR_OP_ENA.
When powering down SPKOUTR,
the SPKR_SPKVDD_ENA bit
should be reset first.
PD, May 2011, Rev 4.1
102
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
