Production Data
WM8912
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
2:0
FLL_FRATIO
[2:0]
111
FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
000 recommended for high FREF
011 recommended for low FREF
Fractional multiply for FREF
(MSB = 0.5)
R118 (76h)
15:0
14:5
3:0
FLL_K [15:0]
FLL_N [9:0]
0000h
177h
0h
FLL Control 3
R119 (77h)
Integer multiply for FREF
(LSB = 1)
FLL Control 4
FLL_GAIN [3:0]
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not
changed from default.
R120 (78h)
4:3
FLL_CLK_REF_
DIV [1:0]
00
FLL Clock Reference Divider
00 = MCLK / 1
FLL Control 5
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must
be divided down to <=13.5MHz.
For lower power operation, the
reference clock can be divided down
further if desired.
1:0
FLL_CLK_REF_
SRC [1:0]
00
FLL Clock source
00 = MCLK
01 = BCLK
10 = LRCLK
11 = Reserved
Table 48 FLL Register Map
FREE-RUNNING FLL CLOCK
The FLL can generate a clock signal even when no external reference is available. However, it
should be noted that the accuracy of this clock is reduced, and a reference source should always be
used where possible. Note that, in free-running mode, the FLL is not sufficiently accurate for hi-fi
DAC applications. However, the free-running mode is suitable for clocking most other functions,
including the Write Sequencer, Charge Pump, DC Servo and Class W output driver.
If an accurate reference clock is available at FLL start-up, then the FLL should be configured as
described above. The FLL will continue to generate a stable output clock after the reference input is
stopped or disconnected.
PD, Rev 4.0, September 2010
73
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
