Production Data
WM8912
DAC OPERATION AT 88.2K / 96K
The WM8912 supports DAC operation at 88.2kHz and 96kHz sample rates. This section details
specific conditions applicable to these operating modes.
For DAC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are
detailed in Table 45. DAC operation at these sample rates is achieved by setting the
SAMPLE_RATE field to half the required sample rate (eg. select 48kHz for 96kHz mode).
For DAC operation at 88.2kHz or 96kHz sample rates, the DAC_OSR128 register must be set to 0.
ReTuneTM Mobile can not be used during 88.2kHz or 96kHz operation, so EQ_ENA must be set to 0.
The SYSCLK frequency is derived from MCLK. The maximum MCLK frequency is defined in the
“Signal Timing Requirements” section.
SAMPLE RATE
REGISTER CONFIGURATION
SAMPLE_RATE = 101
CLOCKING RATIO
88.2kHz
SYSCLK = 128 x fs
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
96kHz
SAMPLE_RATE = 101
SYSCLK = 128 x fs
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
Table 45 DAC Operation at 88.2kHz and 96kHz Sample Rates
PD, Rev 4.0, September 2010
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