WM8912
Production Data
If no reference clock is available at the time of starting up the FLL, then an internal clock frequency
of approximately 12MHz can be generated by enabling the FLL Analogue Oscillator using the
FLL_OSC_ENA register bit, and setting FOUT clock divider to divide by 8 (FLL_OUTDIV = 07h), as
defined in Table 48. Under recommended operating conditions, the FLL output may be forced to
approximately 12MHz by then enabling the FLL_FRC_NCO bit and setting FLL_FRC_NCO_VAL to
19h (see Table 49). The resultant SYSCLK delivers the required clock frequencies for the Class W
output driver, DC Servo, Charge Pump and other functions. Note that the value of
FLL_FRC_NCO_VAL may be adjusted to control FOUT, but care should be taken to maintain the
correct relationship between SYSCLK and the aforementioned functional blocks.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R248 (F8h)
5:0
FLL_FRC_NCO
_VAL [5:0]
01_1001
FLL Forced oscillator value
FLL NCO Test 1
Valid range is 000000 to 111111
0x19h (011001) = 12MHz approx
(Note that this field is required for
free-running FLL modes only)
R247 (F7h)
0
FLL_FRC_NCO
0
FLL Forced control select
0 = Normal
FLL NCO Test 0
1 = FLL oscillator controlled by
FLL_FRC_NCO_VAL
(Note that this field is required for
free-running FLL modes only)
Table 49 FLL Free-Running Mode
In both cases described above, the FLL must be selected as the SYSCLK source by setting
SYSCLK_SRC (see Table 39). Note that, in the absence of any reference clock, the FLL output is
subject to a very wide tolerance. See “Electrical Characteristics” for details of the FLL accuracy.
EXAMPLE FLL CALCULATION
To generate 12.288 MHz output (FOUT) from a 12.000 MHz reference clock (FREF):
•
•
•
•
•
•
•
•
•
Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz:
FLL_CLK_REF_DIV = 00 (divide by 1)
Set FLL_CTRL_RATE to the recommended setting:
FLL_CTRL_RATE = 000 (divide by 1)
Sett FLL_GAIN to the recommended setting:
FLL_GAIN = 0000 (multiply by 1)
Set FLL_OUTDIV for the required output frequency as shown in Table 46:-
F
OUT = 12.288 MHz, therefore FLL_OUTDIV = 07h (divide by 8)
Set FLL_FRATIO for the given reference frequency as shown in Table 47:
REF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1)
F
Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:-
FVCO = 12.288 x 8 = 98.304MHz
Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF):
N.K = 98.304 / (1 x 12) = 8.192
Determine FLL_N and FLL_K from the integer and fractional portions of N.K:-
FLL_N is 8. FLL_K is 0.192
Confirm that N.K is a fractional quantity and set FLL_FRACN_ENA:
N.K is fractional. Set FLL_FRACN_ENA = 1.
Note that, if N.K is an integer, then an alternative value of FLL_FRATIO should be
selected in order to produce a fractional value of N.K.
PD, Rev 4.0, September 2010
74
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
