Production Data
WM8912
GPIO OUTPUTS FROM FLL
The WM8912 has an internal signal which indicates whether the FLL Lock has been achieved. The
FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt
event - see “Interrupts”.
The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See
“General Purpose Input/Output (GPIO)” for details of how to configure a GPIO pin to output the FLL
Lock signal.
The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the
FLL Clock may be output even if the FLL is not selected as the WM8912 SYSCLK source. The
clocking configuration is illustrated in Figure 44. See “General Purpose Input/Output (GPIO)” for
details of how to configure a GPIO pin to output the FLL Clock.
EXAMPLE FLL SETTINGS
Table 50 provides example FLL settings for generating common SYSCLK frequencies from a variety
of low and high frequency reference inputs.
FREF
FOUT
FLL_CLK_
REF_DIV
FVCO
FLL_N
FLL_K
FLL_
FRATIO
FLL_
OUTDIV
FLL_
FRACN
_ENA
32.768
kHz
12.288
Divide by 1
(0h)
98.304
187
0.5
16
8
1
MHz
MHz
(0BBh)
344
(8000h)
0.5
(4h)
8
(7h)
8
32.768
kHz
11.288576
MHz
Divide by 1
(0h)
90.308608
MHz
1
1
0
1
1
0
1
1
1
1
1
(158h)
344
(8000h)
0.53125
(8800h)
0
(3h)
8
(7h)
8
32.768
kHz
11.2896
MHz
Divide by 1
(0h)
90.3168
MHz
(158h)
256
(3h)
8
(7h)
8
48
12.288
MHz
Divide by 1
(0h)
98.304
MHz
kHz
(100h)
8
(0000h)
0.192
(3h)
1
(7h)
8
12.000
MHz
12.288
MHz
Divide by 1
(0h)
98.3040
MHz
(008h)
7
(3127h)
0.526398
(86C2h)
0
(0h)
1
(7h)
8
12.000
MHz
11.289597
MHz
Divide by 1
(0h)
90.3168
MHz
(007h)
8
(0h)
1
(7h)
8
12.288
MHz
12.288
MHz
Divide by 1
(0h)
98.304
MHz
(008h)
7
(0000h)
0.35
(0h)
1
(7h)
8
12.288
MHz
11.2896
MHz
Divide by 1
(0h)
90.3168
MHz
(007h)
7
(599Ah)
0.56184
(8FD5h)
0.94745
(F28Ch)
0.119995
(1EB8h)
0.703995
(B439h)
(0h)
1
(7h)
8
13.000
MHz
12.287990
MHz
Divide by 1
(0h)
98.3040
MHz
(007h)
6
(0h)
1
(7h)
8
13.000
MHz
11.289606
MHz
Divide by 1
(0h)
90.3168
MHz
(006h)
5
(0h)
1
(7h)
8
19.200
MHz
12.287988
MHz
Divide by 2
(1h)
98.3039
MHz
(005h)
4
(0h)
1
(7h)
8
19.200
MHz
11.289588
MHz
Divide by 2
(1h)
90.3168
MHz
(004h)
(0h)
(7h)
Table 50 Example FLL Settings
PD, Rev 4.0, September 2010
75
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
