WM8912
Production Data
DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R22 (16h)
3
OPCLK_ENA
0
GPIO Clock Output Enable
0 = disabled
Clock Rates 2
1 = enabled
R26 (1Ah)
11:8
OPCLK_DIV [3:0]
0000
GPIO Output Clock Divider
0000 = SYSCLK
Audio
Interface 2
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
Table 42 OPCLK Control
TOCLK CONTROL
A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input de-
bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA,
and its frequency is controlled by TOCLK_RATE and TOCLK_RATE_X4, as described in Table 43.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R22 (16h)
12
TOCLK_RATE
0
TOCLK Rate Divider (/2)
0 = f / 2
Clock Rates 2
1 = f / 1
0
TOCLK_ENA
0
0
0
Zero Cross timeout enable
0 = Disabled
1 = Enabled
R20 (14h)
Clock Rates 0
14
13
TOCLK_RATE_
DIV16
TOCLK Rate Divider (/16)
0 = f / 1
1 = f / 16
TOCLK_RATE_
X4
TOCLK Rate Multiplier
0 = f x 1
1 = f x 4
Table 43 TOCLK Control
A list of possible TOCLK rates is provided in Table 44.
TOCLK
TOCLK_RATE
TOCLK_RATE_X4 TOCLK_RATE_DIV16
FREQ
(Hz)
PERIOD
(ms)
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1000
500
1
0
2
1
250
4
0
125
8
1
62.5
16
32
64
128
0
31.25
15.625
7.8125
1
0
Table 44 TOCLK Rates
PD, Rev 4.0, September 2010
68
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
