Production Data
WM8912
Figure 44 Clocking Scheme
SYSCLK CONTROL
The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either the
selected MCLK source or the FLL output. The MCLK source can be inverted or non-inverted, as
selected by the MCLK_INV bit. The selected source may also be adjusted by the MCLK_DIV divider
to generate SYSCLK. These register fields are described in Table 39. See “Frequency Locked Loop
(FLL)” for more details of the Frequency Locked Loop clock generator.
The SYSCLK signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 0 when
reconfiguring clock sources. It is not recommended to change SYSCLK_SRC while the
CLK_SYS_ENA bit is set.
The following operating frequency limits must be observed when configuring SYSCLK. Failure to
observe these limits will result in degraded noise performance and/or incorrect DAC functionality.
.
.
.
.
SYSCLK ≥ 3MHz
If DAC_OSR128 = 1 then SYSCLK ≥ 6MHz
If DAC_MONO = 1, then SYSCLK ≥ 64 x fs
If DAC_MONO = 0, then SYSCLK ≥ 128 x fs
Note that DAC Mono mode (DAC_MONO = 1) is only valid when one or other DAC is disabled. If
both DACs are enabled, then the minimum SYSCLK for clocking the DACs is 128 x fs.
PD, Rev 4.0, September 2010
65
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