WM8904
Pre-Production
DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
Enables HPL input stage
0 = Disabled
4
HPL_ENA
0
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPL
Enable sequence.
Removes HPR short
0 = HPR short enabled
1 = HPR short removed
3
2
1
HPR_RMV_SHO
RT
0
0
0
For normal operation, this bit should
be set as the final step of the HPR
Enable sequence.
Enables HPR output stage
0 = Disabled
HPR_ENA_OUTP
HPR_ENA_DLY
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
Enables HPR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPR_ENA.
Enables HPR input stage
0 = Disabled
0
HPR_ENA
0
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPR
Enable sequence.
PP, Rev 3.3, September 2012
74
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
