WM8904
Pre-Production
OUTPUT MUX CONTROL
By default, the DAC outputs are routed directly to the respective output PGAs. A multiplexer (mux) is
provided on each output path to select the BYPASSL or BYPASSR analogue signals from the
Left/Right Input PGAs in place of the DAC outputs.
The output multiplexers are configured using the register bits described in Table 44.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R61 (3Dh)
Analogue
OUT12 ZC
Selects input for left headphone
output MUX
3
HPL_BYP_ENA
0
0 = Left DAC
1 = Left input PGA (Analogue
bypass)
Selects input for right headphone
output MUX
2
1
0
HPR_BYP_ENA
0
0
0
0 = Right DAC
1 = Right input PGA (Analogue
bypass)
Selects input for left line output
MUX
LINEOUTL_BYP_
ENA
0 = Left DAC
1 = Left input PGA (Analogue
bypass)
Selects input for right line output
MUX
LINEOUTR_BYP_
ENA
0 = Right DAC
1 = Right input PGA (Analogue
bypass)
Table 44 Output Mux Control
OUTPUT VOLUME CONTROL
Each analogue output can be independently controlled. The headphone output control fields are
described in Table 45. The line output control fields are described in Table 46. The output pins are
described in more detail in “Analogue Outputs”.
The volume and mute status of each output can be controlled individually using the bit fields shown in
Table 45 and Table 46.
To prevent “zipper noise” when a volume adjustment is made, a zero-cross function is provided on all
output paths. When this function is enabled, volume updates will not take place until a zero-crossing
is detected. In the event of a long period without zero-crossings, a timeout will apply. The timeout
must be enabled by setting the TOCLK_ENA bit, as defined in “Clocking and Sample Rates”.
The volume update bits control the loading of the output driver volume data. For example, when
HPOUT_VU is set to 0, the headphone volume data can be loaded into the respective control
register, but will not actually change the gain setting. The Left and Right headphone volume settings
are updated when a 1 is written to HPOUT_VU. This makes it possible to update the gain of a
Left/Right pair of output paths simultaneously.
PP, Rev 3.3, September 2012
76
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
