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WM8904CGEFL/V 参数 Datasheet PDF下载

WM8904CGEFL/V图片预览
型号: WM8904CGEFL/V
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗编解码器用于便携式音频应用 [Ultra Low Power CODEC for Portable Audio Applications]
分类和应用: 解码器编解码器电信集成电路便携式PC
文件页数/大小: 188 页 / 1824 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8904  
Pre-Production  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Removes LINEOUTL short  
REFER TO  
Pop Suppression  
Control  
R94 (5Eh)  
Analogue  
Lineout 0  
7
LINEOUTL_RM  
V_SHORT  
0
0 = LINEOUTL short enabled  
1 = LINEOUTL short removed  
For normal operation, this bit should be set as the  
final step of the LINEOUTL Enable sequence.  
Enables LINEOUTL output stage  
0 = Disabled  
Pop Suppression  
Control  
6
5
LINEOUTL_ENA  
_OUTP  
0
0
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
Enables LINEOUTL intermediate stage  
0 = Disabled  
Pop Suppression  
Control  
LINEOUTL_ENA  
_DLY  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the output signal path has been configured, and  
before DC offset cancellation is scheduled. This bit  
should be set with at least 20us delay after  
LINEOUTL_ENA.  
Enables LINEOUTL input stage  
0 = Disabled  
Pop Suppression  
Control  
4
3
2
1
LINEOUTL_ENA  
0
0
0
0
1 = Enabled  
For normal operation, this bit should be set as the  
first step of the LINEOUTL Enable sequence.  
Removes LINEOUTR short  
0 = LINEOUTR short enabled  
1 = LINEOUTR short removed  
Pop Suppression  
Control  
LINEOUTR_RM  
V_SHORT  
For normal operation, this bit should be set as the  
final step of the LINEOUTR Enable sequence.  
Enables LINEOUTR output stage  
0 = Disabled  
Pop Suppression  
Control  
LINEOUTR_EN  
A_OUTP  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
Enables LINEOUTR intermediate stage  
0 = Disabled  
Pop Suppression  
Control  
LINEOUTR_EN  
A_DLY  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the output signal path has been configured, and  
before DC offset cancellation is scheduled. This bit  
should be set with at least 20us delay after  
LINEOUTR_ENA.  
Enables LINEOUTR input stage  
0 = Disabled  
Pop Suppression  
Control  
0
LINEOUTR_EN  
A
0
1 = Enabled  
For normal operation, this bit should be set as the  
first step of the LINEOUTR Enable sequence.  
Register 5Eh Analogue Lineout 0  
PP, Rev 3.3, September 2012  
166  
w
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