Pre-Production
WM8904
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
FLL Fractional enable
REFER TO
R116 (74h)
FLL Control
1
2
FLL_FRACN_E
NA
0
Frequency Locked
Loop (FLL)
0 = Integer Mode
1 = Fractional Mode
Fractional Mode (FLL_FRACN_ENA=1) is
recommended in all cases
FLL Oscillator enable
0 = Disabled
1
FLL_OSC_ENA
0
Frequency Locked
Loop (FLL)
1 = Enabled
FLL_OSC_ENA must be enabled before enabling
FLL_ENA.
Note that this field is required for free-running FLL
modes only.
FLL Enable
0 = Disabled
1 = Enabled
0
FLL_ENA
0
Frequency Locked
Loop (FLL)
FLL_OSC_ENA must be enabled before enabling
FLL_ENA.
Register 74h FLL Control 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
FLL FOUT clock divider
00_0000 = Reserved
00_0001 = Reserved
00_0010 = Reserved
00_0011 = 4
R117 (75h)
FLL Control
2
13:8
FLL_OUTDIV
[5:0]
00_0000
Frequency Locked
Loop (FLL)
00_0100 = 5
00_0101 = 6
…
11_1110 = 63
11_1111 = 64
(FOUT = FVCO / FLL_OUTDIV)
Frequency of the FLL control block
000 = FVCO / 1 (Recommended value)
001 = FVCO / 2
6:4
FLL_CTRL_RAT
E [2:0]
000
Frequency Locked
Loop (FLL)
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
111 = FVCO / 8
Recommended that these are not changed from
default.
F
VCO clock divider
2:0
FLL_FRATIO
[2:0]
111
Frequency Locked
Loop (FLL)
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 8
PP, Rev 3.3, September 2012
169
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
