WM8904
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
1XX = divide by 16
000 recommended for FREF > 1MHz
100 recommended for FREF < 64kHz
Register 75h FLL Control 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Fractional multiply for FREF
(MSB = 0.5)
Frequency Locked
Loop (FLL)
R118 (76h)
FLL Control
3
15:0
FLL_K [15:0]
0000_0000_0
000_0000
Register 76h FLL Control 3
REGISTER
ADDRESS
BIT
14:5
3:0
LABEL
DEFAULT
DESCRIPTION
REFER TO
Integer multiply for FREF
(LSB = 1)
Frequency Locked
Loop (FLL)
R119 (77h)
FLL Control
4
FLL_N [9:0]
01_0111_0
111
FLL Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
Frequency Locked
Loop (FLL)
FLL_GAIN [3:0]
0000
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not changed from
default.
Register 77h FLL Control 4
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
FLL Clock Reference Divider
00 = MCLK / 1
Frequency Locked
Loop (FLL)
R120 (78h)
FLL Control
5
4:3
FLL_CLK_REF_
DIV [1:0]
00
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must be divided
down to <=13.5MHz.
For lower power operation, the reference clock can
be divided down further if desired.
FLL Clock source
00 = MCLK
Frequency Locked
Loop (FLL)
1:0
FLL_CLK_REF_
SRC [1:0]
00
01 = BCLK
10 = LRCLK
11 = Reserved
Register 78h FLL Control 5
PP, Rev 3.3, September 2012
170
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
