Pre-Production
WM8904
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Enables HPOUTR intermediate stage
0 = Disabled
Pop Suppression
Control
1
HPR_ENA_DLY
0
1 = Enabled
For normal operation, this bit should be set to 1 after
the output signal path has been configured, and
before DC offset cancellation is scheduled. This bit
should be set with at least 20us delay after
HPR_ENA.
Enables HPOUTR input stage
0 = Disabled
Pop Suppression
Control
0
HPR_ENA
0
1 = Enabled
For normal operation, this bit should be set as the
first step of the HPR Enable sequence.
Register 5Ah Analogue HP 0
PP, Rev 3.3, September 2012
165
w