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WM8904CGEFL/V 参数 Datasheet PDF下载

WM8904CGEFL/V图片预览
型号: WM8904CGEFL/V
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗编解码器用于便携式音频应用 [Ultra Low Power CODEC for Portable Audio Applications]
分类和应用: 解码器编解码器电信集成电路便携式PC
文件页数/大小: 188 页 / 1824 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8904  
Pre-Production  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
DC Servo DAC Write status  
REFER TO  
DC Servo  
7:4  
DCS_DAC_WR_  
COMPLETE [3:0]  
0000  
[3] - LINEOUTR  
[2] - LINEOUTL  
[1] - HPOUTR  
[0] - HPOUTL  
0 = DAC Write DC Servo mode not completed.  
1 = DAC Write DC Servo mode complete.  
DC Servo Start-Up status  
[3] - LINEOUTR  
DC Servo  
3:0  
DCS_STARTUP  
_COMPLETE  
[3:0]  
0000  
[2] - LINEOUTL  
[1] - HPOUTR  
[0] - HPOUTL  
0 = Start-Up DC Servo mode not completed..  
1 = Start-Up DC Servo mode complete.  
Register 4Dh DC Servo Readback 0  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
Removes HPOUTL short  
0 = HPOUTL short enabled  
1 = HPOUTL short removed  
Pop Suppression  
Control  
R90 (5Ah)  
Analogue  
HP 0  
7
HPL_RMV_SHO  
RT  
0
For normal operation, this bit should be set as the  
final step of the HPL Enable sequence.  
Enables HPOUTL output stage  
0 = Disabled  
Pop Suppression  
Control  
6
5
HPL_ENA_OUT  
P
0
0
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
Enables HPOUTL intermediate stage  
0 = Disabled  
Pop Suppression  
Control  
HPL_ENA_DLY  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the output signal path has been configured, and  
before DC offset cancellation is scheduled. This bit  
should be set with at least 20us delay after  
HPL_ENA.  
Enables HPOUTL input stage  
0 = Disabled  
Pop Suppression  
Control  
4
3
2
HPL_ENA  
0
0
0
1 = Enabled  
For normal operation, this bit should be set as the  
first step of the HPL Enable sequence.  
Removes HPOUTR short  
0 = HPOUTR short enabled  
1 = HPOUTR short removed  
Pop Suppression  
Control  
HPR_RMV_SHO  
RT  
For normal operation, this bit should be set as the  
final step of the HPR Enable sequence.  
Enables HPOUTR output stage  
0 = Disabled  
Pop Suppression  
Control  
HPR_ENA_OUT  
P
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
PP, Rev 3.3, September 2012  
164  
w
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