WM8850
Pre-Production
When the LINKED_MODE bit is set in the S/PDIF Verb, the S/PDIF Tx 1 output is synchronised to the
S/PDIF Rx input stream. In this mode, the SRC_BASE register field should be set to match the base
rate frequency of the Input Sample Rate. The SRC_MULT and SRC_DIV fields can be used to select
a range of S/PDIF Tx1 output sample rates which are synchronous to the received S/PDIF Rx sample
rate. Figure 20 shows a simplified diagram:
Figure 20 S/PDIF Transmit - Linked Mode
S/PDIF TRANSMIT WITHOUT USING SRC2
When SRC2 is not enabled, the output sample rate of the S/PDIF stream is controlled directly from
Stream Format Verb. Figure 21 shows a simplified diagram:
Figure 21 S/PDIF Transmit without SRC2
PP, April 2011, Rev 3.2
70
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
