Pre-Production
WM8850
The Digital Converter Verb is supported by the S/PDIF Tx 1 node, allowing selected channel status
information as defined in the HDA Specification to be set. It is also possible to set the remaining bits
of channel status data as defined in IEC-60958-3, using the vendor-specific Tx Channel Status
Control Verb.
SET VERB
BIT
BITFIELD
NAME
DEFAULT
DESCRIPTION
784h
7:4
Channel
Status
0h
Original Sampling Frequency
[39:36]
3:1
Channel
Status
5h
Sample Word Length
[35:33]
0
Channel
1
Max Word Length
Status [32]
783h
7:6
Channel
Status
0h
Channel Status [31:30]
[31:30]
5:4
3:0
7:4
3:0
7:4
Channel
Status
[29:28]
0h
1h
0h
0h
0h
Clock Accuracy
Channel
Status
[27:24]
Sampling Frequency
782h
781h
Channel
Status
[23:20]
Channel Number for Sub-Frame B
Channel Number for Sub-Frame A
Source Number
Channel
Status
[23:20]
Channel
Status
[19:16]
3:2
1:0
Channel
Status [7:6]
0h
0h
Channel Status Mode
Channel
Additional De-emphasis information
Status [5:4]
Notes:
1. See IEC-60958-3 for full definitions of the channel status bits
2. The channel number of Sub-Frame B is uniquely configuration – all other channel status bits in
Sub-Frame B have the same value as Sub-Frame A
3. Remaining channel status bits are set using the Digital Converter Verb as per the HDA
Specification
PP, April 2011, Rev 3.2
67
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
