Pre-Production
WM8850
S/PDIF TRANSMIT USING SRC2
The WM8850 provides a full-range sample rate converter, SRC2, to interface between the HDA link
domain and the S/PDIF transmitter (S/PDIF Tx 1) domain. SRC2 is implemented as a processing
function within the S/PDIF Tx 1 node, and so is enabled by the Processing State Verb as defined in
the HDA Specification.
When SRC2 is enabled, it is configured automatically by the WM8850, using the Stream Format Verb
for the input sample rate, and the vendor-specific S/PDIF Verb for the output. Figure 19 shows a
simplified diagram to demonstrate this:
Figure 19 S/PDIF Transmit using SRC2
Note that the SRC2 Sample Rate Converter is associated with the S/PDIF Tx 1 node only; there is no
SRC associated with S/PDIF Tx 2.
Note that, when SRC2 is enabled, the output S/PDIF stream will always contain 24-bit data.
The vendor-specific S/PDIF Verb implemented in the S/PDIF Tx 1 node is described below.
When SRC2 is enabled, the lock status is reported using the SRC_LOCK bit. When SRC2 is
unlocked, it will output zero samples at the rate programmed by the Stream Format Verb. When
SRC2 gains lock, transmission of valid samples will begin.
The LINKED_MODE bit provides the option to synchronise the S/PDIF Tx 1 output with the S/PDIF
Rx input stream. Further details of this function are provided below.
GET VERB
BIT
BITFIELD
NAME
DEFAULT
DESCRIPTION
F80h
8
SRC_LOCK
SRC_BASE
SRC_MULT
0
SRC2 lock flag:
0 = SRC2 unlocked
1 = SRC2 locked
7
0
Used to set the base rate frequency:
0 = 48 kHz
1 = 44.1 kHz
6:4
0h
Used to set the base rate multiplication factor:
0h = x1 (48 kHz, 44.1 kHz or less)
1h = x2 (96 kHz, 88.2 kHz, 32 kHz)
2h = Reserved
3h = x4 (192 kHz, 176.4 kHz)
4h-7h = Reserved
3:1
SRC_DIV
0h
Used to set the base rate division factor:
0h = divide by 1 (48 kHz, 44.1 kHz)
1h = Reserved
2h = divide by 3 (32 kHz)
3h-7h= Reserved
0
LINKED_
MODE
0
Linked mode control:
0 = Linked mode disabled
1 – Linked mode enabled
PP, April 2011, Rev 3.2
69
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
