WM8850
Pre-Production
Channel Number for Sub-Frame B
782h
781h
7:4
3:0
7:4
Channel
Status
[23:20]
0h
0h
0h
Channel
Status
[23:20]
Channel Number for Sub-Frame A
Source Number
Channel
Status
[19:16]
3:2
1:0
Channel
Status [7:6]
0h
0h
Channel Status Mode
Channel
Additional De-emphasis information
Status [5:4]
Notes:
1. See IEC-60958-3 for full definitions of the channel status bits
2. The channel number ofr Sub-Frame B is uniquely configuration – all other channel status bits in
Sub-Frame B have the same value as Sub-Frame A
3. Remaining channel status bits are set using the Digital Converter Verb as per the HDA
Specification
Under default conditions, the WM8850 will pack the S/PDIF Tx Channel Status Data with the correct
values of Sampling Frequency and Sample Word Length automatically, taking into account the
various routing options through the chip. This means the Channel Status Data always reflects the
same rate as the physical S/PDIF stream.
If required, this behaviour can be disabled using the vendor-specific Channel Status Data Packing
Configuration Verb. When CSD_MODE is set to 0, the S/PDIF Tx Channel Status Data is completely
defined using the vendor-specifc Tx Channel Status Control Verb.
SET VERB
BIT
BITFIELD
NAME
DEFAULT
DESCRIPTION
785h
0
CSD_MODE
1
S/PDIF Transmitter Channel Status Data
Packing Mode:
0 = Manual mode: sample rate and data width
channel status data packed from data sourced
from the Tx Channel Status Control Verb
1 = Automatic mode: sample rate and data
width channel status data packed from data
sourced from the Stream Verb, S/PDIF Verb or
S/PDIF Rx Rate Detector (depending on
routing through device)
PP, April 2011, Rev 3.2
72
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
