Pre-Production
WM8850
S/PDIF RECEIVE USING SRC1
The WM8850 provides a full-range sample rate converter, SRC1, to interface between the S/PDIF
receiver domain and the HDA link domain. SRC1 is implemented as a processing function within the
S/PDIF Rx node, and so is enabled by the Processing State Verb as defined in the HDA
Specification.
When SRC1 is enabled, it is configured automatically by the WM8850, using the recovered sample
rate for the S/PDIF stream for the input sample rate, and the Stream Format Verb for the output
sample rate. Figure 15 shows a simplified diagram to demonstrate this.
Figure 15 S/PDIF Receive using SRC1
When SRC1 is enabled, the lock status is reported using the vendor-specific S/PDIF Verb supported
by the S/PDIF Rx node (NID = 05h).
GET VERB
BIT
BITFIELD
NAME
DEFAULT
DESCRIPTION
F80h
8
SRC_LOCK
0
SRC1 lock flag:
0 = SRC1 unlocked
1 = SRC1 locked
When SRC1 is unlocked, it will output zero samples at the rate programmed by the Stream Format
Verb. When SRC1 gains lock, transmission of valid samples will begin.
S/PDIF RECEIVE WITHOUT USING SRC1
When SRC1 is not enabled, the Stream Format Verb becomes read-only, and is set according to the
recovered sample rate. Figure 16 shows a simplified diagram of this configuration.
Figure 16 S/PDIF Receive without SRC1
PP, April 2011, Rev 3.2
63
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
