Pre-Production
WM8850
Floating point conversion is implemented in all Converter widgets. The conversion is enabled when
the Stream Format Verb for the widget node has Bits set to 4 (for 32-bit formatting).
AUDIO WIDGETS CAPABILITIES PARAMETER: DIGITAL
The MIC1 audio path can begin at either Port-B (Analogue Microphone) or Port-D (Digital
Microphone). This leads to some confusion when setting the Widget Capability Parameter. Bit [9] of
this parameter is called Digital and is used to indicate if the widget acts on an analogue stream or on
a digital stream.
In the cases of the MIC1 Converter (NID = 03h) and the MIC1 Mux (NID = 09h), these can act on both
analogue or digital streams, depending on which microphone interface is being used. For these two
nodes, Digital = 0 to indicate that the nodes act on analogue data, but the user should be aware that
these nodes can also act on digital data when the digital microphone is being used.
The Port-D node has its Digital parameter set to 1 to indicate that it acts on digital data.
LATENCY
The group delay or latency for an audio path varies based on sample rate and processing steps (e.g.
SRC). As variable reporting is not supported as part of the Intel HDA Specification, the Delay
parameter in the Audio Widgets Capabilities Parameter is set to 0 to indicate that latency is not
reported.
POWER STATES
Within the AFG, all power states are supported. These are interpreted as follows:
D0: Fully on
D1: Link active, Jack detection logic on, analogue references enabled, but converters and
DSP logic still disabled.
D2: Link active, Jack detection logic on, register read/write access possible but all modules
in an audio path are disabled.
D3: Link disabled (i.e. BCLK stopped), responses not possible but Jack detection logic on
and capable of issuing a wake.
D4: Power applied, and settings maintained. Jack detection logic off, and wake disabled.
The AFG node supports the Power State verb. Widget nodes also offer power control, but their
settings are restricted to select only power states below that of the AFG power state setting. For
example, if the AFG node is set at D1, widget nodes can be set to D1, D2, D3, but not D0.
The default power state of the AFG is D2 so as to allow the PLLs to lock during CODEC initialisation.
The default power state of the widget nodes is D3 so as to minimise power consumption. Widget
nodes do not support D4 as the D3 state is identical to D4 at the widget node level.
Power state transitions are done in sequence. For example, if a node is in power state D3, and the
power state is set to D0, the transitions steps are D3-D2-D1-D0. If a Get Power State command is
issued during the state transitions, the actual power state returned, will be the power state at the end
of the frame that the Power State command was issued in.
It is possible that the actual power state returned is D3, D2 or D0 while the set power state returned is
D0.
For low power operation, the link should be in the Link Reset state and the WM8850 AFG should be
in D3 or D4. If the link is in the Link Reset state, and the WM8850 AFG was left in states D0, D1 or
D2, the WM8850 cannot issue a power state changes request (i.e. wake).
The only settings that can be changed in the D4 state is the AFG Power State or AFG reset settings –
any other changes will be ignored.
PP, April 2011, Rev 3.2
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
