WM8850
Pre-Production
In D3, BCLK may be stopped after the WM8850 asserts the PS-ClkStopOK register in the AFG’s
Power State verb. The PS-ClkStopOK bit will remain asserted in power state D3 until the power state
is modified to D0, D1 or D2. If the power state is changed to D4 while in power state D3 when the
PS-ClkStopOK bit is set, software must poll the AFG PS-Act bits to determine when the WM8850
reports transition to power state D4 complete (and hence reports PS-Act as D4) before stopping the
BCLK.
In D3, if the link is not in the Link Reset state and BCLK is running, the WM8850 will issue an
unsolicited response rather than a wake.
In D3 (with the link is the Link Reset state), the WM8850 is capable of generating a wake (i.e. a power
state change request). The Controller will respond to the wake by putting the WM8850 through an
initialisation sequence. The initialisation sequence will not change the register settings, so the
WM8850 will still report a power state of D3 but the WM8850 will be able to send responses, including
any unsolicited response(s) that caused a wake to be issued.
As register settings are maintained in the D3/D4 states, the user should be aware that if the WM8850
is brought from D3/D4 to D0 and stream IDs had been previously assigned, data rendering and
capture will commence. If this behaviour is not desired, the user should bring the WM8850 to state
D3 and set the stream IDs to 0, or ensure that stream IDs are set to 0 prior to entering the D3/D4
state.
STREAM START/STOP
Sections 4.5.3 and 4.5.4 of the Intel HD Audio specification describe the starting and stopping of
streams. While the descriptions are sufficient from a controller perspective, there are ambiguities from
a CODEC perspective.
For each stream that goes through the HDA Link, there is a ‘Stream Manager’ module within the
WM8850 whose function is to assemble/disassemble the stream packets within the link frame. The
Stream Manager is disabled while the Stream value in the Converter Stream, Channel Verb is set to
0h. When disabled, the captured data will not be sent on the link, and data from the link will not be
decoded for rendering.
For audio path configuration, it is assumed that the Stream ID is the last register to be set in the
configuration sequence. When Stream ID is set to a non-zero value it has the effect of starting the
stream. On starting the stream, Stream Managers associated with input converters begin transmitting
data on the link, and Stream Managers associated with output converters begin to decode data with
the corresponding stream tag.
Note: Audio paths with mute capabilities may have ‘un-mute’ as the final configuration step. For
these paths, the stream will have started but the audio data will be zeroed until mute has been
disabled.
There are test paths within the WM8850 that do not use the HDA Link. These paths can still be used
when the Stream Manager is disabled.
The Stream Manager is also disabled when the associated converter widget is in power state D1, D2
or D3. Digital converters (i.e. S/PDIF) have a DigEn register bit. When this is set to 0, the associated
stream manager is disabled.
It is assumed that the settings of the Stream Format Verb and Converter Stream, Channel Verb will
not change when a stream is active (with the exception of changing the Stream ID to 0 to terminate
the stream). Changing stream settings while a stream is active is an erroneous action, and may
result in audio corruption.
SDI STREAM ORDER
The order of stream transmission on the SDI link is governed by the CODEC. The WM8850 will
transmit streams with the lowest stream ID value first.
If a stream is started with a stream ID lower than an existing stream, then the new stream is
transmitted earlier in the frame than the existing stream (i.e. the WM8850 auto-shuffles the stream
placement within the frame). This moves the existing stream to further on in the frame than it was
prior to the starting of the new stream. It is assumed that moving streams within a frame is
acceptable to the Controller.
PP, April 2011, Rev 3.2
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