Production Data
WM8805
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7
PLL5
07h
1:0
MODE[1:0]
10
PLL Post-scale Divider Select
Selects the PLL output divider value in
conjunction with MCLKDIV and CLKOUTDIV.
Refer to Table 23 for details of FREQMODE
operation.
Note: FREQMODE[1:0] bits are
automatically set in S/PDIF Receive Mode.
2
FRACEN
1
Integer/Fractional PLL Mode Select
0 = Integer PLL (PLL_N value used, PLL_K
value ignored)
1 = Fractional PLL (both PLL_N and PLL_K
values used)
Note: FRACEN must be set to enable the
fractional PLL when using S/PDIF Receive
Mode.
3
MCLKDIV
0
MCLK Divider Select
(Only valid when CLK2 is selected as MCLK
output source)
See Table 23 for MCLKDIV configuration in
PLL user mode.
See Table 28 for MCLKDIV configuration in
PLL S/PDIF receive mode.
5:4
CLKOUTDIV[1:0]
01
CLKOUT Divider Select
(Only valid when CLK1 is selected as CLKOUT
output source)
See Table 27 for CLKOUTDIV[1:0]
configuration in PLL user mode.
See Table 28 for CLKOUTDIV[1:0]
configuration in PLL S/PDIF receive mode.
PD Rev 4.1 September 07
55
w