WM8805
Production Data
CHANNEL STATUS DATA
The channel status bits are recovered from the incoming data stream and are used to control various
functions of the device.
The S/PDIFRx interface always receives 24 bits of data in bits 4 to 27 of the SPDIF payload. The
audio sample can be either 20 bits if AUX bits not used or up to 24bits if AUX bits used. So the audio
sample can be 20,21,22,23 or 24 bit. The source (wherever the S/PDIF data is coming from) of the
S/PDIF data stream must set the MAXWL and RXWL within the status bits to indicate the size of the
audio sample. This is then recovered by the S/PDIF Rx interface. The S/PDIF Rx interface ALWAYS
receives 24 bits, but if the actual length of the audio data sample (indicated by MAXWL and RXWL)
is less than 24 bits, then the user has the option to truncate these 24 bits to the actual size. These
truncated bits are then sent to either the SPDIF Tx or the AIF. Truncation may allow users to process
data faster. If the user does not want this truncation to happen then they must mask the truncation
using the WL_MASK. In this case all 24 bits of data received are transferred.
The audio data sample can be transferred to either the AIF or the SPDIF Tx.
When the audio data sample is transferred to the AIF, and if the AIF is operating in a mode which
has less data bits, then the WM8805 will reduce the audio data sample to the length of the AIF. For
example, if the AIF is operating in 16 bit mode, but the SPDIF Rx receives an audio data sample
length of 21 bits, then the WM8805 will reduce the 21 bits to 16 bits by removing the LSBs. This
cannot be masked. If the AIF is operating in 24 bit mode, then the full 21 bits are transferred on the
AIF, with the LSBs set to 000.
When the audio data sample is transferred to the SPDIF TX, then the full audio data sample (24 bits)
is written to the SPDIF Tx. Unless it has been truncated using the WL-MASK bits.
It is assumed that the channel status is stereo and hence only channel one data is read. The channel
status data is stored in five read-only registers which can be read back over the serial interface (see
Serial Interface Read-back). The CSUD interrupt is asserted when the recovered channel status data
is different to that currently stored in the read only registers. The registers are updated and the
interrupt is asserted when the last bit of channels status data is recovered. The interrupt will remain
asserted until one of the channel status registers is read. If another change to channel status data
occurs before the last block has been read, the interrupt will de-assert when the first bit of differing
channel status is received and will be asserted again when the last bit of the current channel status
block is received.
The register descriptions for the channel status bits are given in Table 40 to Table 44.
PD Rev 4.1 September 07
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
