WM8805
Production Data
REGISTER
ADDRESS
BIT
LABEL
CHANNEL
STATUS
BIT
DEFAULT
DESCRIPTION
R16
RXCHAN4
10h
3:0
FREQ[3:0]
27:24
0001
Indicated Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3)
for full details.
5:4
CLKACU[1:0]
29:28
11
Clock Accuracy of Received Clock
00 = Level II
(read-only)
01 = Level I
10 = Level III
11 = Interface frame rate not matched to
sampling frequency.
Table 43 S/PDIF Receiver Channel Status Register 4
REGISTER
ADDRESS
BIT
LABEL
CHANNEL
STATUS
BIT
DEFAULT
DESCRIPTION
R17
RXCHAN5
11h
0
MAXWL
32
1
Maximum Audio Sample Word Length
0 = 20 bits
1 = 24 bits
(read-only)
Note: see table in description of bits 3:1 of
this register,
3:1
RXWL[2:0]
35:33
000
Audio Sample Word Length
000: Word Length Not Indicated
RXWL[2:0]
001
MAXWL==1
20 bits
MAXWL==0
16 bits
010
22 bits
18 bits
100
23 bits
19 bits
101
24 bits
20 bits
110
21 bits
17 bits
All other combinations are reserved and may
give erroneous operation. Data will be
truncated internally when these bits are set
unless WL_MASK is set. See note 1.
7:4
ORGSAMP
[3:0]
39:36
0000
Original Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3)
for full details.
Table 44 S/PDIF Receiver Channel Status Register 5
Note 1: MAXWL and RXWL[2:0] bits in recovered channel status data are used to truncate digital audio
interface transmitted data. Truncation replaces the lower data bits with 0. Truncation can be masked using
the WL_MASK control bit. Truncation can be masked by the WL_MASK. Refer to received channel status bit
description
PD Rev 4.1 September 07
38
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
