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WM8802
PLL LOCK
ERROR
INPUT PARITY
ERROR (A)
INPUT PARITY
ERROR (B)
INPUT PARITY
ERROR (C)
DATA
RDATA output
fs calculation result
Channel status
Validity flag
Low
Low
Low
Low
Low
Low
Output
Low
Previous value data
Output
Output
Output
Previous value data
Output
Previous value data
Output
Low
User data
Low
Output
Output
Table 11 Data Processing upon Error Occurrence
Notes:
1. Input parity error (A): Occurs 9 or more times in succession
2. Input parity error (B): Occurs 8 or fewer times in succession, in case of audio data
3. Input parity error (C): Occurs 8 or fewer times in succession, in case of non-PCM burst data
Figure 20 shows an example of data processing upon occurrence of a parity error.
An error occurs a single time
Input Data
RERR
L-1
R-1 L-2 R-2 L-3 R-3 L-4 R-4 L-5 R-5 L-6 R-6 L-7 R-7 L-8 R-8
RLRCK
RDATA
L-0 R-0 L-1 R-0 L-2 R-2 L-2 R-2 L-2 R-2 L-2 R-2 L-2 R-2
R-ch L-ch R-ch …. Muted after 9 or more
Previous data value Previous data value consecutive errors
Figure 20 Data Processing Upon Parity Error Occurrence
PROCESSING DURING ERROR RECOVERY
PLL becomes locked and data demodulation begins when preambles B, M and W are detected.
RDATA output data is output from the RLRCK edge after RERR goes Low.
PP Rev 1.1 April 2004
29
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
