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WM8802
SDIN
[RDTSEL]
[TDTSEL]
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RDATA
RXOUT
TXO
MUX
DIR
(8in / 2out)
DIT
TDATA
Figure 19 Data Block Diagram
CALCULATION OF INPUT DATA SAMPLING FREQUENCY
The input data sampling frequency is calculated using the XIN clock.
When the oscillation amplifier automatically stops during PLL lock, the input data sampling frequency
is calculated during the RERR error period. The calculation is completed at the same time that the
oscillation amplifier stops. The value remains unchanged until the PLL becomes unlocked.
In the mode where the oscillation amplifier operates continuously, calculation processing is
performed continuously The calculation results (which follows the input data) can be read even if
sampling rate is changed within the PLL capture range, but only for a signal where channel status
sampling information does not change,.
The calculation result can be read from CCB address 0xEB and output to registers DO4 to DO7 and
DO8 to DO15. Registers DO4 through DO7 hold the encoded result, while DO8 through DO15 hold
the calculation value. The sampling frequencies that can be calculated are greater than 24kHz as the
calculation count value is output in 8-bit units. For details, see section Micro-controller Interface.
ERROR OUTPUT PROCESSING
LOCK ERROR, DATA ERROR OUTPUT (RERR)
An error flag RERR is output when a PLL lock error or a data error occurs.
Non-PCM data reception can be treated as an error with the RESEL setting.
The RERR output conditions are set using RESTA. Since the PLL status can be output at any time,
the PLL status can be monitored even when the clock source is XIN.
PP Rev 1.1 April 2004
27
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
