WM8802
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OUTPUT DATA SWITCHING (SDIN, RDATA)
RDATA demodulation data is output when the PLL is locked and the SDIN input is selected This
switching is automatically performed according to the locked/unlocked status of the PLL. For details,
see the timing charts below.
Switch to a clock source synchronized to the SDIN data when SDIN input data is selected.
The SDIN input data can be output to RDATA regardless of the locked/unlocked status of the PLL
using RDTSTA setting.
The RDATA output data can be forcibly muted using the RDTMUT setting.
The PLL continues operating when the clock source is set to XIN using OCKSEL and RCKSEL as
long as its operation is not stopped using PLLOPR. The PLL status is continuously output from
RERR as long as error output is not forcibly set with RESTA. The processed information can also be
read with the micro-controller interface regardless of the PLL status.
PLL locked status
UNLOCK
LOCK
CKST
RERR
RDATA
Demodulation data
SDIN data
Muted
(a) Lock-in stage
LOCK
PLL locked status
CKST
UNLOCK
Muted
RERR
Demodulation data
RDATA
SDIN data
(b) Unlock stage
Figure 18 RDATA Output Data Switch Timing Chart
DATA BLOCK DIAGRAM (RX0 TO RX6, TX0, RXOUT, TDATA, RDATA, SDIN)
The RDATA output data is switched to SDIN input data using RDTSEL.
The SDIN input data can be input to the modulation function using TDTSEL.
The modulation output is an input to the Input Switch Multiplexer and can be output from RXOUT. It
is possible to use a signal that has been digitized with an A/D converter for digital recording output,
etc. using this function.
PP Rev 1.1 April 2004
26
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
