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WM8802
SDIN (1)
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
1/fs
LEFT
CHANNEL
RIGHT
CHANNEL
RLRCK (0)
RBCK (0)
1
2
3
n
RDATA (0)
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
16 to 24 bits
16 to 24 bits
Figure 16 Serial Audio Data Input Timing – Left Justified
SDIN (1)
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
1/fs
LEFT
RIGHT
CHANNEL
CHANNEL
RLRCK (0)
RBCK (0)
RDATA (0)
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
16,20,24 bits
16,20,24 bits
Figure 17 Serial Audio Data Input Timing – Right Justified
PP Rev 1.1 April 2004
25
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