欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8802SCFV 参数 Datasheet PDF下载

WM8802SCFV图片预览
型号: WM8802SCFV
PDF下载: 下载PDF文件 查看货源
内容描述: 数字音频接口收发器 [Digital Audio Interface Transceiver]
分类和应用:
文件页数/大小: 65 页 / 516 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8802SCFV的Datasheet PDF文件第17页浏览型号WM8802SCFV的Datasheet PDF文件第18页浏览型号WM8802SCFV的Datasheet PDF文件第19页浏览型号WM8802SCFV的Datasheet PDF文件第20页浏览型号WM8802SCFV的Datasheet PDF文件第22页浏览型号WM8802SCFV的Datasheet PDF文件第23页浏览型号WM8802SCFV的Datasheet PDF文件第24页浏览型号WM8802SCFV的Datasheet PDF文件第25页  
Product Preview  
WM8802  
BI-PHASE SIGNAL INPUT / OUTPUT  
BI-PHASE SIGNAL INPUT RECEPTION RANGE  
The input data reception range depends on the PLL lock frequency setting set by PLLSEL. The  
relationship between this setting and the guaranteed reception range is shown below.  
PLL OUTPUT CLOCK SETTING  
512fs (PLLSEL = 0)  
INPUT DATA RECEPTION RANGE  
28kHz to 105kHz  
256fs (PLLSEL = 1)  
28kHz to 195kHz  
Table 10 Relationship Between PLL Output Clock Setting and Reception Range  
(FSLIM[0:1] = 0)  
The fs reception range for input data within the above PLL output clock setting range can be  
controlled. This setting is performed using FSLIM[0:1]. When this function is used, input data that  
exceeds the setting range is considered as an error and the clock source is automatically switched to  
the XIN source. The RDATA output data then depends on the RDTSEL setting.  
BI-PHASE SIGNAL INPUT/OUTPUT PINS (RX0 TO RX6, RXOUT)  
There are 7 digital data input pins. Data modulated with the modulation function can also be  
selected, therefore selection from a total of 8 signals is possible. However, the pins that can be  
selected are restricted by the following conditions:  
1. The six pins RX0 and RX2 to RX6 are TTL level input pins with 5V input level tolerable.  
2. RX1 is a coaxial-compatible input pin with built-in amplifier that can receive up to 200mVp-p  
data.  
The demodulation input and RXOUT output signals can also be selected independently.  
1. The demodulation data is selected with RISEL[0:2].  
2. The RXOUT output data is selected with ROSEL[0:2].  
RXOUT can be muted with RXOFF. Muting is recommended when not using RXOUT in order to  
reduce clock jitter.  
The data input status can be monitored with the RXMON setting. The status of each data input pin is  
stored in CCB address 0xEA and output registers DO0 to DO7. Since this function uses the XIN  
clock, the oscillation amplifier must be set to the continuous operation mode when RXMON is set.  
Demodulation input pin switching can be performed during PLL unlock using the ULSEL setting. As a  
result, data switching can be accurately communicated to peripheral devices.  
The interval from pin switching through RISEL[0:2] until data is received is about 250µs to 350µs.  
This function also requires that the oscillation amplifier is set to the continuous operation mode.  
Input pin selection  
RX0  
RX2  
RX3  
RX1  
Internal supply signal  
RX0  
RX2  
RX3  
RX1  
250µs to 350µs  
Figure 9 Input Pin Selection Processing via PLL Unlock  
PP Rev 1.1 April 2004  
21  
w
 复制成功!