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WM8802
OUTPUT CLOCKS (RMCK, RBCK, RLRCK, SBCK, SLRCK)
The WM8802 features two clock systems in order to supply the various clocks for the A/D converter,
DSP and other peripheral devices.
The clock output settings for the R and S systems are set using PRSEL[0:1], XRSEL[0:1],
XRBCK[0:1], XRLRCK[0:1], PSBCK[0:1], PSLRCK[0:1], XSBCK[0:1], and XSLRCK[0:1].
(a)
(1)
(2)
(3)
(4)
(5)
Setting range for clock output pins when using the PLL source
RMCK: 1/1, 1/2, and 1/4 of 512fs or 256fs
RBCK: 64fs output
RLRCK: fs output
SBCK: 128fs, 64fs, and 32fs
SLRCK: 2fs, fs, and fs/2
(b)
(1)
(2)
(3)
(4)
(5)
Setting range for clock output pins when using the XIN source
RMCK: 1/1, 1/2, and 1/4 of 12.288MHz or 24.576MHz
RBCK: 12.288MHz, 6.144MHz, and 3.072MHz
SBCK: 12.288MHz, 6.144MHz, and 3.072MHz
RLRCK: 192kHz, 96kHz, and 48kHz
SLRCK: 192kHz, 96kHz, and 48kHz
The polarity of RBCK, RLRCK, SBCK and SLRCK can be reversed with RBCKP, RLRCKP, SBCKP
and SLRCKP.
Clock switching is processed on the rising edge of the RLRCK output after the falling edge of micro-
controller interface CE.
TMCK
PLL SOURCE
XIN SOURCE
SOURCE
256fs
256fs
OUTPUT PIN NAME
RMCK
512fs
256fs
256fs
128fs
64fs
12.288MHz 24.576MHz
12.288MHz 24.576MHz
6.144MHz 12.288MHz
512fs
256fs
128fs
128fs
64fs
3.072MHz
6.144MHz
12.288MHz
RBCK
64fs
fs
6.144MHz
3.072MHz
192kHz
RLRCK
96kHz
48kHz
128fs
64fs
32fs
2fs
12.288MHz
6.144MHz
3.072MHz
192kHz
SBCK
SLRCK
fs
96kHz
fs/2
48kHz
Table 9 Output Clock Frequencies (Bold Items = Initial Settings)
PP Rev 1.1 April 2004
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
