WM8802
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CLOCK SWITCH TRANSITION SIGNAL OUTPUT ( CKST )
CKST outputs Low when the output clock changes during PLL lock/unlock.
In the lock-in stage (PLL locked following the detection of input data) the CKST Low pulse falls at
the word clock edge generated from the XIN clock. The CKST Low pulse rises at the same timing as
RERR following the lapse of a given period.
In the unlock stage, the CKST Low pulse falls at the same timing as the PLL lock detection signal
RERR and rises following a given number of word clocks generated from the XIN clock.
The PLL lock status change and clock change timing is detected by the rising and falling edges of
the CKST Low pulse.
Digital Data
RX0 to RX6
Unlock
Lock
Locked status
XTAL Clock
VCO Clock
45 ms to 300 ms
Same timing as
RERR
After PLL lock
CKST
RERR
RMCK
(a) Lock-in stage
RX0 to RX6
Digital Data
Lock
Unlock
Locked status
XTAL Clock
VCO Clock
CKST
0.6 ms to 6.4 ms
Same timing as RERR
RERR
RMCK
(b) Unlock stage
Figure 8 Clock Switch Timing
PP Rev 1.1 April 2004
20
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
