WM8776
Production Data
REGISTER
ADDRESS
BIT
LABEL
RAG[7:0]
DEFAULT
DESCRIPTION
R15 (0Fh)
0001111
7:0
11001111
(0dB)
Attenuation data for right channel ADC gain in 0.5dB steps.
00000000 : digital mute
00000001 : -103dB
………..
Attenuation
ADCR
11001111 : 0dB
…………
11111110 : +23.5dB
11111111 : +24dB
8
ZCRA
0
Right ADC zero cross enable:
0: Zero cross disabled
1: Zero cross enabled
Limiter threshold/ALC target level in 1dB steps
0000: -16dB FS
R16 (10h)
0010000
3:0
LCT[3:0]
1011
(-5dB)
ALC Control 1
0001: -15dB FS
…
1101: -3dB FS
1110: -2dB FS
1111: -1dB FS
6:4
MAXGAIN[2:0]
111
(+24dB)
Set Maximum Gain of PGA
111 : +24dB
110 : +20dB
….(-4dB steps)
010 : +4dB
001 : 0dB
000 : 0dB
8:7
LCSEL[1:0]
HLD[3:0]
00
ALC/Limiter function select
00 = Limiter
(Limiter)
01 = ALC Right channel only
10 = ALC Left channel only
11 = ALC Stereo (PGA registers unused)
ALC hold time before gain is increased.
0000: OFF
R17 (11h)
0010001
3:0
0000
(OFF)
ALC Control 2
0001: 2.67ms
0010: 5.33ms
… (time doubles with every step)
1111: 43.691s
7
ALCZC
LCEN
0 (zero
cross off)
ALC uses zero cross detection circuit.
8
0
Enable Gain control circuit.
0 = Disable
1 = Enable
PD Rev 4.0 April 2005
46
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
