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WM8776_05 参数 Datasheet PDF下载

WM8776_05图片预览
型号: WM8776_05
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz立体声编解码器与5频道I / P多路复用器 [24-bit, 192kHz Stereo CODEC with 5 Channel I/P Multiplexer]
分类和应用: 解码器复用器编解码器
文件页数/大小: 57 页 / 601 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8776_05的Datasheet PDF文件第40页浏览型号WM8776_05的Datasheet PDF文件第41页浏览型号WM8776_05的Datasheet PDF文件第42页浏览型号WM8776_05的Datasheet PDF文件第43页浏览型号WM8776_05的Datasheet PDF文件第45页浏览型号WM8776_05的Datasheet PDF文件第46页浏览型号WM8776_05的Datasheet PDF文件第47页浏览型号WM8776_05的Datasheet PDF文件第48页  
WM8776  
Production Data  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
DAC Interface format select  
R10 (0Ah)  
0001010  
1:0  
DACFMT[1:0]  
10  
00: right justified mode  
01: left justified mode  
10: I2S mode  
DAC Interface  
Control  
11: DSP mode  
2
DACLRP  
0
DACLRC Polarity or DSP Early/Late mode select  
Left Justified / Right Justified /  
I2S  
DSP Mode  
0: Early Mode  
1: Late Mode  
0: Standard DACLRC Polarity  
1: Inverted DACLRC Polarity  
DAC BITCLK Polarity  
3
DACBCP  
0
0: Normal – DIN and DACLRC sampled on rising edge of  
DACBCLK.  
1: Inverted - DIN and DACLRC sampled on falling edge of  
DACBCLK.  
5:4  
DACWL[1:0]  
10  
DAC Input Word Length  
00: 16-bit Mode  
01: 20-bit Mode  
10: 24-bit Mode  
11: 32-bit Mode (not supported in right justified mode)  
R11 (0Bh)  
0001011  
1:0  
ADCFMT[1:0]  
ADCLRP  
10  
0
ADC Interface format select  
00: right justified mode  
01: left justified mode  
10: I2S mode  
ADC Interface  
Control  
11: DSP mode  
2
ADCLRC Polarity or DSP Early/Late mode select  
Left Justified / Right Justified /  
I2S  
DSP Mode  
0: Early Mode  
0: Standard ADCLRC Polarity  
1: Inverted ADCLRC Polarity  
1: Late Mode  
3
ADCBCP  
0
ADC BITCLK Polarity  
0: Normal - ADCLRC sampled on rising edge of  
ADCBCLK; DOUT changes on falling edge of ADCBCLK.  
1: Inverted - ADCLRC sampled on falling edge of  
ADCBCLK; DOUT changes on rising edge of ADCBCLK.  
5:4  
ADCWL[1:0]  
10  
ADC Input Word Length  
00: 16-bit Mode  
01: 20-bit Mode  
10: 24-bit Mode  
11: 32-bit Mode (not supported in right justified mode)  
6
8
ADCMCLK  
ADCHPD  
0
0
ADCMCLK Polarity:  
0: non-inverted  
1: inverted  
ADC Highpass Filter Disable:  
0: Highpass Filter enabled  
1: Highpass Filter disabled  
PD Rev 4.0 April 2005  
44  
w
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