Product Preview
WM8773
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
10100
Mute
5
RECEN
0
REC Output Enable
0 : REC output muted
1: REC output enabled
Interface format select
1:0
FMT[1:0]
10
10110
00: right justified mode
01: left justified mode
10: I2S mode
Interface
Control
11: DSP mode
2
LRP
0
ADCLRC Polarity or DSP Early/Late mode select
Left Justified / Right Justified /
I2S
DSP Mode
0: Early DSP mode
1: Late DSP mode
0: Standard ADCLRC Polarity
1: Inverted ADCLRC Polarity
BITCLK Polarity
3
BCP
0
0: Normal - ADCLRC sampled on rising edge of BCLK;
DOUT changes on falling edge of BCLK.
1: Inverted - ADCLRC sampled on falling edge of BCLK;
DOUT changes on rising edge of BCLK.
5:4
WL[1:0]
10
Input Word Length
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
ADC Highpass Filter Disable:
0: Highpass Filter enabled
8
ADCHPD
0
1: Highpass Filter disabled
10111
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC ratio select:
010: 256fs
Master Mode
control
011: 384fs
100: 512fs
3
8
0
1
ADCOSR
MS
0
0
0
1
ADC oversample rate select
0: 128x oversampling
1: 64x oversampling
Maser/Slave interface mode select
0: Slave Mode – ADCLRC and BCLK are inputs
1: Master Mode – ADCLRC and BCLK are outputs
Chip Powerdown Control (works in together with ADCD)
0: All circuits running, outputs are active
1: All circuits in power save mode, outputs muted
ADC powerdown:
11000
PWDN
ADCD
Powerdown
Control
0: ADC enabled
1: ADC disabled
11001
4:0
5
LAG[4:0]
MUTE
01100
(0dB)
0
Attenuation data for left channel ADC gain in 1dB steps
Attenuation
ADCL
Mute for Left channel ADC:
0: Mute off
1: Mute on
6
7
LRBOTH
0
0
Setting LRBOTH will write the same gain value to LAG[4:0] and
RAG[4:0]
ADCMUTE
Mute for Left and Right channel ADC:
0: Mute off
1: Mute on
PP Rev 1.0 June 2002
23
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
