WM8772EFT – 32 LEAD TQFP
Production Data
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCBCLK/DACBCLK cycle
time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
ADCBCLK/DACBCLK pulse
width high
ADCBCLK/DACBCLK pulse
width low
ADCLRC/DACLRC set-up
time to
tLRSU
ADCBCLK/DACBCLK rising
edge
ADCLRC/DACLRC hold
time from
tLRH
10
ns
ADCBCLK/DACBCLK rising
edge
DIN1/2/3 set-up time to
DACBCLK rising edge
tDS
tDH
tDD
10
10
0
ns
ns
ns
DIN1/2/3 hold time from
DACBCLK rising edge
DOUT propagation delay
10
from ADCBCLK falling edge
Table 15 Digital Audio Data Timing – Slave Mode
MPU INTERFACE TIMING
tCSL
tCSH
ML/I2S
tSCY
tCSS
tSCS
tSCH
tSCL
MC/IWL
MD/DM
LSB
tDSU
tDHO
Figure 42 SPI Compatible Control Interface Input Timing
PD Rev 4.2 October 2005
46
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
