WM8772EDS – 28 LEAD SSOP
Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
LRC
BCLK
DOUT
WM8772
CODEC
DSP
ENCODER/
DECODER
DIN1/2/3
3
Figure 16 Audio Interface – Slave Mode
tBCH
tBCL
BCLK
tBCY
LRC
tLRSU
tDS
tLRH
DIN1/2/3
tDD
tDH
DOUT
Figure 17 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRC set-up time to BCLK
rising edge
tLRSU
LRC hold time from BCLK
rising edge
tLRH
tDS
10
10
10
ns
ns
ns
DIN1/2/3 set-up time to
BCLK rising edge
DIN1/2/3 hold time from
BCLK rising edge
tDH
PD Rev 4.2 October 2005
18
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
