WM8772EDS – 28 LEAD SSOP
Production Data
PAGES 12 TO 36 DESCRIBE THE OPERATION OF THE WM8772EDS
28 LEAD SSOP PRODUCT VARIANT.
PAGES 37 TO 66 DESCRIBE THE OPERATION OF THE WM8772EFT
32 LEAD TQFP PRODUCT VARIANT.
WM8772EDS – 28 LEAD SSOP
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 13 ADC and DAC Master Clock Timing Requirements
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width
high
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
28
40:60
60:40
Table 2 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
LRC
DSP/
ENCODER/
DECODER
WM8772
CODEC
DOUT
DIN1/2/3
3
Figure 14 Audio Interface - Master Mode
PD Rev 4.2 October 2005
16
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
