Production Data
WM8772EDS – 28 LEAD SSOP
BCLK
(Output)
tDL
LRC
(Output)
tDDA
DOUT
DIN1/2/3
tDST
tDHT
Figure 15 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRC propagation delay from
BCLK falling edge
tDL
0
0
10
10
ns
ns
ns
ns
DOUT propagation delay
from BCLK falling edge
tDDA
tDST
tDHT
DIN1/2/3 setup time to
BCLK rising edge
10
10
DIN1/2/3 hold time from
BCLK rising edge
Table 3 Digital Audio Data Timing – Master Mode
PD Rev 4.2 October 2005
17
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