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WM8772_05 参数 Datasheet PDF下载

WM8772_05图片预览
型号: WM8772_05
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz的6通道编解码器,带有音量控制 [24-bit, 192kHz 6-Channel Codec with Volume Control]
分类和应用: 解码器编解码器
文件页数/大小: 73 页 / 758 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8772EDS – 28 LEAD SSOP  
Production Data  
The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes  
the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low  
again allows data into the filter.  
The automute function detects a series of ZERO value audio samples of 1024 samples long being  
applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire  
OR’ed through a 10kresistor to the MUTE pin. Thus if the MUTE pin is not being driven, the  
automute function will assert mute.  
If MUTE is tied low, AUTOMUTED is overridden and will not mute unless the IZD register bit is set. If  
MUTE is driven from a bi-directional source, then both MUTE and automute functions are available. If  
MUTE is not driven, AUTOMUTED appears as a weak output (10ksource impedance) and can be  
used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives  
a non-ZERO input.  
A diagram showing how the various Mute modes interact is shown below Figure 20.  
IZD (Register Bit)  
AUTOMUTED  
(Internal Signal)  
10k  
SOFTMUTE  
(Internal  
Signal)  
MUTE  
PIN  
MUTE (Register Bit)  
Figure 20 Selection Logic for MUTE Modes  
INPUT FORMAT SELECTION  
In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type  
and input data word length for both the ADC and DAC.  
ML/I2S  
MC/IWL  
INPUT DATA MODE  
24-bit right justified  
0
0
1
0
1
0
20-bit right justified  
16-bit I2S  
24-bit I2S  
1
1
Table 8 Input Format Selection  
Note:  
In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (LRC)  
are high for a minimum of 24 bit clocks (BCLK) and low for a minimum of 24 bit clocks.  
DE-EMPHASIS CONTROL  
In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to  
be applied.  
MD/DM  
DE-EMPHASIS  
0
Off  
On  
1
Table 9 De-emphasis Control  
PD Rev 4.2 October 2005  
22  
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