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WM8771
ADC INPUT GAIN
Registers LAG and RAG control the left and right channel gain into the stereo ADC in 1dB steps from
+19dB to –12dB Table 8 shows how the attenuation levels are selected from the 5-bit words.
L/RAG[6:0]
ATTENUATION LEVEL
0
-12dB
:
:
0dB
:
01100
:
11111
+19dB
Table 11 ADC gain control
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
REGISTER ADDRESS
BIT
8
LABEL
DEFAULT
0
DESCRIPTION
10110
ADCHPD
ADC Highpass filter disable:
0: Highpass filter enabled
1: Highpass filter disabled
ADC control
ADC INPUT MUX AND POWERDOWN CONTROL
REGISTER
ADDRESS
BIT
2:0
6:4
8
LABEL
LMX[2:0]
RMX[2:0]
AINPD
DEFAULT
DESCRIPTION
11011
ADC mux and
powerdown
control
000
000
1
ADC left channel input mux control
bits (see Figure 35)
ADC right channel input mux
control bits (see Figure 35)
Input mux and buffer powerdown
0: Input mux and buffer
enabled
1: Input mux and buffer
powered down
Register bits LMX and RMX control the left and right channel inputs into the stereo ADC. The default
is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 8-channel
mux inputs are switched to buffered VMIDADC.
LMX[2:0]
LEFT ADC INPUT
RMX[2:0]
RIGHT ADC INPUT
000
001
010
011
100
101
110
111
AIN1L
AIN2L
AIN3L
AIN4L
AIN5L
AIN6L
AIN7L
AIN8L
000
001
010
011
100
101
110
111
AIN1L
AIN2L
AIN3L
AIN4L
AIN5L
AIN6L
AIN7R
AIN8R
Table 12 ADC input mux control
PP Rev 2.0 December 2001
31
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
